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Fig: Circuit Diagram for Mod 6 Counter. WORKING: Mod 6 counter should count from initial state 0 up to 5.Circuit diagram for Mod 6 counter is shown above. After 5 counter enters state 6 ,it should reset to state 0. Here mod 2 and mod 5 are cascaded i.e. Clk B is connected to Qa. s1 and s2 are not used so they are connected to the ground. When counter enters state no.6 Qa and Qd will become '0' and Qb and Qc becomes '1'.i.e.In binary 6 is written as 0110 ,so we count bits from Qd to Qa(from right to left). The AND gate input is given to r1 and r2 ,and the counter will be reset. For mod 9,Qa and Qd wil be '1' ,Qb and Qc will be '0'.
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